1. Field of the Invention
The present invention relates to a semiconductor device and an information processing system including the same, and more particularly to a semiconductor device that can verify whether a control signal supplied from outside, such as a command signal, has proper logic and an information processing system including the same.
2. Description of Related Art
Semiconductor memory devices typified by a dynamic random access memory (DRAM) receive an address signal and a command signal supplied from a controller, and access their memory cell array based on the signals. More specifically, an address signal supplied to a semiconductor memory device is latched into an address latch circuit, and memory cells to be accessed are identified based on the address signal. A command signal supplied to the semiconductor memory device is decoded by a command decoder, and an access type (whether the access is a read operation, a write operation, etc.) is identified based on the command signal (see Japanese Patent Application Laid-Open No. 2011-81893).
DDR4 (Double Data Rate 4) DRAMs have recently been proposed as DRAMs even faster than DDR3 (Double Data Rate 3) DRAMs. DDR4 DRAMs support a new function called “CA parity”. The CA parity refers to the function of verifying whether an address signal and a command signal supplied from a controller have proper logic. Such a function can be used to detect inversion of logic of bits constituting the address signal and the command signal, i.e., a parity error occurring during transmission if any.
What processing to perform on the DRAM side in the event of a parity error is important in view of improving the reliability of semiconductor devices in practical use. DRAMs that can perform appropriate processing in the event of a parity error are demanded. Such a demand is not only on DDR4 DRAMs but also on semiconductor devices in general that can verify control signals supplied from outside.